Inside the New IBM/Sony/Toshiba Cell Processor
What a week for tech news. Here's a great look at the archtecture of the much anticipated Cell CPU from IBM, Sony and Toshiba. ArsTechnica has a good look at the way the new CPU works:

"The basic architecture of the Cell is described by IBM as a "system on a chip" (SoC) design. This is a perfectly good characterization, but I'd take it even further and call Cell a "network on a chip." As I described yesterday, the Cell's eight SPUs are essentially full-blown vector "computers," insofar as they are fairly simple CPUs with their own local storage. These small vector computers are connected to each other and to the 512KB L2 cache via a element interface bus (EIB) that consists of four sixteen-byte data rings with 64-bit tags. This bus can transfer 96 bytes/cycle, and can handle over 100 outstanding requests.

"The individual SPEs can use this bus to communicate with each other, and this includes the transfer of data in between SPEs acting as peers on the network. The SPEs also communicate with the L2 cache, with main memory (via the MIC), and with the rest of the system (via the BIC). The onboard memory interface controller (MIC) supports the new Rambus XDR memory standard, and the BIC (which I think stands for "bus interface controller" but I'm not 100% sure) has a coherent interface for SMP and a non-coherent interface for I/O."

Required Reading:
--Read the Complete Ars Technica Piece Here
--More on the Cell (624 Articles from Google News)
--Sony to use the Cell in the Playstation 3


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